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december 2011 doc id 019056 rev 3 1/20 20 STEF12 electronic fuse for 12 v line features continuous current (typ): 3.6 a n-channel on-resistance (typ): 53 m enable/fault functions output clamp voltage (typ):15 v undervoltage lockout short-circuit limit overload current limit controlled output voltage ramp thermal latch (typ): 165 c uses tiny capacitors operating junction temp. - 40 c to 125 c available in dfn10 (3 x 3 mm) package applications hard disk drives solid state drives (ssd) hard disk and ssd arrays set-top boxes dvd and blu-ray disc drivers description the STEF12 is an integrated electronic fuse optimized for monitoring output current and input voltage. connected in series to a 12 v rail, it is capable of protecting the electronic circuitry on its output from overcurrent and overvoltage. the device has a controlled delay and turn-on time. when an overload condition occurs, the STEF12 limits the output current to a predefined safe value. if the anomalous overload condition persists it goes into an open state, disconnecting the load from the power supply. if a continuous short-circuit is present on the board, when power is re-applied the e-fuse initially limits the output current to a safe value and then again goes into an open state. the device is equipped with a thermal protection circuit. the intervention of the thermal protection is signalled to the board monitoring circuits through a signal on the fault pin. unlike the mechanical fuses, which must be physically replaced after a single event, the e- fuse does not degrade in its performance after short-circuit/thermal protection interventions and it is reset either by recycling the supply voltage or using the enable pin. the companion chip for the 5 v power rails is also available with part number stef05. dfn10 (3 x 3 mm) table 1. device summary order code package packaging STEF12pur dfn10 (3 x 3 mm) tape and reel www.st.com
contents STEF12 2/20 doc id 019056 rev 3 contents 1 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.1 turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.2 normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.3 output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.4 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1.5 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 r limit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 c dv/dt calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 enable/fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STEF12 device block diagram doc id 019056 rev 3 3/20 1 device block diagram figure 1. STEF12 block diagram am09 8 91v1
pin configuration STEF12 4/20 doc id 019056 rev 3 2 pin configuration figure 2. pin configuration (top view) v cc s o u rce s o u rce s o u rce s o u rce s o u rce gnd dv/dt en/f au lt i-limit n/c am09 88 0v1 table 2. pin description pin n symbol note 1 gnd ground pin 2dv/dt the internal dv/dt circuit controls the slew rate of the output volt age at turn-on. the internal capacitor allows a ramp-up time of around 1ms. an external capacitor can be added to this pin to increase the ramp time. if an additional capacitor is not required, this pin should be left open. 3 en/fault the enable/fault pin is a tri-state, bi-direction al interface. during normal operation the pin must be left floating, or it can be used to di sable the output of the device by pulling it to ground using an open drain or open collector device. if a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a monitor circuit that the device is in thermal shutdown. it can be connected to another device of this family to cause a simultaneous shutdown during thermal events. 4 i-limit a resistor between this pin and the source pi n sets the overload and short-circuit current limit levels. 5 nc not connected 6 to 10 v out /source connected to the source of the internal po wer mosfet and to the out put terminal of the fuse 11 v cc exposed pad. positive input voltage must be connected to v cc .
STEF12 maximum ratings doc id 019056 rev 3 5/20 3 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings symbol parameter value unit v cc positive power supply voltage (steady state) -0.3 to 18 v positive power supply voltage (max 100ms) -0.3 to 25 v out /source (max 100ms) -0.3 to vcc+0.3 v i-limit (max 100ms) -0.3 to 25 v en/fault -0.3 to 7 v dv/dt -0.3 to 7 v t op operating junction temperature range (1) -40 to 125 c t stg storage temperature range -65 to 150 c t lead lead temperature (soldering) 10 sec 260 c 1. the thermal limit is set above the maxi mum thermal rating. it is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time. table 4. thermal data symbol parameter value unit r thja thermal resistance junction-ambient 52.7 c/w r thjc thermal resistance junction-case 17.4 c/w table 5. esd performance symbol parameter test conditions value unit esd esd protection hbm 1 kv mm 200 v cdm 500 v
electrical characteristics STEF12 6/20 doc id 019056 rev 3 4 electrical characteristics v cc = 12 v, v en = 3.3 v, c i = 10 f, c o = 47 f, t j = 25 c (unless otherwise specified). table 6. electrical characteristics for STEF12 symbol parameter test cond itions min. typ. max. unit under/overvoltage protection v clamp output clamping voltage v cc = 18 v 13.8 15 16.2 v v uvlo undervoltage lockout turn-on, voltage rising 7.7 8.5 9.3 v v hyst uvlo hysteresis 0.80 v power mosfet t dly delay time enabling of chip to i d = 100 ma with a 1 a resistive load 350 s r dson on-resistance (1) 35 53 70 m - 40 c < t j < 125 c (2) 82 v off off state output voltage v cc = 18 v, v gs = 0, r l = infinite 40 100 mv i d continuous current 0.5in 2 pad, t a = 25 c (1) 3.6 a minimum copper, t a = 80 c 1.7 current limit i short short-circuit current limit r limit = 22 3.3 4.4 5.5 a i lim overload current limit r limit = 22 4.4 a dv/dt circuit dv/dt output voltage ramp time enable to v out = 11.7 v, no c dv/dt 0.5 0.9 2.6 ms enable/fault v il low level input voltage out put disabled 0.35 0.58 0.81 v v i(int) intermediate level input voltage thermal fault, output disabled 0.82 1.4 1.95 v v ih high level input voltage output enabled 1.96 2.64 3.3 v v i(max) high state maximum voltage 3.4 4.3 5.4 v i il low level input current (sink) v enable = 0 v -10 -30 a i i high level leakage current for external switch v enable = 3.3 v 1 a maximum fan-out for fault signal total numbers of chips that can be connected to this pin for simultaneous shutdown 3units total device i bias bias current device operational 1.5 2 ma thermal shutdown 1
STEF12 electrical characteristics doc id 019056 rev 3 7/20 v min minimum operating voltage 7.6 v thermal latch tsd shutdown temperature (1) 165 c 1. pulse test: pulse width = 300 s, duty cycle = 2% 2. guaranteed by design, but not tested in production table 6. electrical characteristics for STEF12 (continued) symbol parameter test cond itions min. typ. max. unit
typical application STEF12 8/20 doc id 019056 rev 3 5 typical application figure 3. application circuit figure 4. typical hdd application circuit 5.1 operating modes 5.1.1 turn-on when the input voltage is applied, the enable/fault pin goes up to the high state, enabling the internal control circuitry. after an initial delay time of typically 350 s, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. if no additional capacitor is connected to dv/dt pin, the total time from the enable signal going high and the output voltage reaching the nominal value is around 1 ms (refer to figure 5, 15 ) am09869v1
STEF12 typical application doc id 019056 rev 3 9/20 5.1.2 normal operating condition the STEF12 e-fuse behaves like a mechanical fuse, buffering the circuitry on its output with the same voltage shown at its input, with a sm all voltage fall due to the n-channel mosfet r dson . 5.1.3 output voltage clamp this internal protection circui t clamps the output voltage to a maximum safe value, typically 15 v, if the input voltage exceeds this threshold. 5.1.4 current limiting when an overload event occurs, the current lim iting circuit reduces th e conductivity of the power mosfet, in order to clamp the output current at the value selected externally by means of the limiting resistor r limit ( figure 3 ). 5.1.5 thermal shutdown if the device temperature exceeds the thermal latch threshold, typically 165 c, the thermal shutdown circuitry turns the power mosfet off, thus disconnecting the load. the en/fault pin of the device is automatically set at an intermediate voltage, in order to signal the overtemperature event. in this condition the e-fuse can be reset either by cycling the supply voltage or by pulling down the en pin below the v il threshold and then releasing it. 5.2 r limit calculation as shown in figure 3 , the device uses an internal n-channel sense fet with a fixed ratio, to monitor the output current and limit it at the level set by the user. the r limit value for achieving the requested current limitation can be estimated by using the following theoretical formula, together with the graph in figure 13: current limit vs. rlimit . equation 1 5.3 c dv/dt calculation connecting a capacitor between the c dv/dt pin and gnd allows the modification of the output voltage ramp-up time. given the desired time interval t during which the output voltage goes from zero to its maximum value, the capacitance to be added on the c dv/dt pin can be calculated using the following theoretical formula: equation 2 where c dv/dt is expressed in farads and the time in seconds. r limit 95 i short -------------- = c dvdt 24 10 9 ? t30x10 12 ? ? =
typical application STEF12 10/20 doc id 019056 rev 3 the addition of an external c dv/dt influences also the initial delay time, defined as the time between the enable signal going high and the start of the v out slope ( figure 5 ) . the contribution of the external capacitor to this time interval can be estimated by using the following theoretical formula: equation 3 figure 5. delay time and v out ramp-up time 5.4 enable/fault pin the enable/fault pin has the dua l function of controlling the out put of the device and, at the same time, of providing information about the device status to the application. when it is used as a standard enable pin, it should be connected to an external open-drain or open-collector device. in this case, when it is pulled at low lo gic level, it turns the output of the e-fuse off. if this pin is left floating, since it has internal pull-up circuitry, the output of the e-fuse is kept on, in normal operating conditions. in case of thermal fault, the pin is pulled to an intermediate state ( figure 6 ). this signal can be provided to a monitor circuit, informing it that a thermal shutdown has occurred, or it can be directly connected to the enable/fault pins of other stefxx devices on the same application in order to achieve a simultaneous enable/disable feature. when a thermal fault occurs, the device can be reset either by cycling the supply voltage or by pulling down the enable pin below the v il threshold and then releasing it. delay time 350 10 6 ? 11.3 10 6 + c dvdt = am09 88 2v1 0 2 4 6 8 10 12 v time en/f au lt vout delay time ramp-up time
STEF12 typical application doc id 019056 rev 3 11/20 figure 6. enable/fault pin status am09 8 71v1 0 1 2 3 4 5 en/fault volta g e [v] time normal operatin g condition thermal fault condition off/re s et
typical performance characteristics STEF12 12/20 doc id 019056 rev 3 6 typical performance characteristics the following plots are referred to the typical application circuit and, unless otherwise noted, at t a = 25 c. figure 7. clamping voltage vs. temperature figure 8. uvlo voltage vs. temperature figure 9. uvlo hysteresis vs. temperature figure 10. off-state voltage vs. temperature figure 11. bias current (device operational) figure 12. on resistance vs. temperature am09 883 v1 1 3 .5 14 14.5 15 15.5 16 16.5 -40 -25 0 25 55 8 5 125 150 o u tp u t volt a ge (v) temper a t u re c v cc = 1 8 v am09 88 4v1 7.5 7.7 7.9 8 .1 8 . 3 8 .5 8 .7 8 .9 9.1 9. 3 9.5 -40 -25 0 25 55 8 5125150 uvlo volt a ge (v) temper a t u re c v cc = from 0 to 12 v, r limit = 15 am09 88 5v1 0.2 0.4 0.6 0. 8 1 1.2 1.4 -40 -25 0 25 55 8 5 125 150 uvlo hy s tere s y s (v) temper a t u re c v cc from 12 to 0 v, r limit = 15 am09 88 6v1 0 50 100 150 200 250 -40 -25 0 25 55 8 5 125 150 o u tp u t volt a ge (mv) temper a t u re c v cc = 1 8 v, v g s = 0, r l = infinite am09 88 7v1 0 0.5 1 1.5 2 2.5 3 -40 -25 0 25 55 8 5 125 150 c u rrent (ma) temper a t u re c v cc = 12 v, r limit = 15 am09 888 v1 20 3 0 40 50 60 70 8 0 90 -40 -25 0 25 55 8 5 125 r d s on (m ) temper a t u re c v cc = 12 v, r limit = 15 , i load = 1 a
STEF12 typical performance characteristics doc id 019056 rev 3 13/20 figure 13. current limit vs. r limit figure 14. thermal latch delay vs. power figure 15. v out ramp-up vs. enable figure 16. v out clamping v cc = 12 v, c in = 10 f, c out = 10 f, r limit = 22 , no c dv/dt, t = 25c v cc = 18 v, c in = 10 f, r limit = 22 , no c dv/dt ,t = 25c figure 17. line transient figure 18. startup into output short-circuit v cc = from 12 to 18 v r limit = 22 ; i out = 500 ma, t rise = 100 s v cc = 12 v, r limit = 22 , v out = connected to gnd am09 88 9v1 v cc = 12 v, t = 25 c 0.00 1.00 2.00 3 .00 4.00 5.00 6.00 7.00 8 .00 9.00 01020 3 040506070 8 0 limit & s hort current (a) external s en s in g re s i s tor ( ) ilim i s hort am09 8 90v1 0. 8 8 8 0 8 00 01020 3 0405060 thermal action time (m s ) power (w) t=25 c t=55 c t= 8 5 c
typical performance characteristics STEF12 14/20 doc id 019056 rev 3 figure 19. thermal latch from 2 a load to short-circuit figure 20. startup into output short-circuit (fast rise) v cc = 12 v, r limit = 22 , v out = connected to gnd
STEF12 package mechanical data doc id 019056 rev 3 15/20 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 7. dfn10l mechanical data dim. mm. inch. min. typ. max. min. typ. max. a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0 0.02 0.05 0 0.001 0.002 a3 0.20 0.008 b 0.18 0.25 0.30 0.007 0.010 0.012 d 2.90 3 3.10 0.114 0.118 0.122 d2 2.23 2.38 2.48 0.088 0.094 0.098 e 2.90 3 3.10 0.114 0.118 0.122 e2 1.49 1.64 1.74 0.059 0.065 0.069 e 0.50 0.020 l 0.30 0.40 0.50 0.012 0.016 0.020
package mechanical data STEF12 16/20 doc id 019056 rev 3 figure 21. dfn10l package outline 8049731/a
STEF12 package mechanical data doc id 019056 rev 3 17/20 dim. mm. inch. min. typ. max. min. typ. max. a1 8 0 7.0 8 7 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 14.4 0.567 ao 3 . 3 0.1 3 0 bo 3 . 3 0.1 3 0 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx ( 3 x 3 ) mechanical data
package mechanical data STEF12 18/20 doc id 019056 rev 3 figure 22. dfn10l footprint - recommended data
STEF12 revision history doc id 019056 rev 3 19/20 8 revision history table 8. document revision history date revision changes 15-jul-2011 1 initial release. 08-aug-2011 2 modified definition for t op in table 3: absolute maximum ratings . 14-dec-2011 3 removed v dv/dt and i dv/dt rows from dv/dt circuit table 6 on page 6 .
STEF12 20/20 doc id 019056 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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